1. Field of the Invention
The present invention relates to a phase locked loop for a communication system and, more particularly, to a phase locked loop for improving a locking time prolonged by a component deviation of a voltage controlled oscillator and deviation caused by variation of circumstances.
2. Description of the Related Art
A phase locked loop (hereinafter, referred to as a PLL) is an automatic control circuit for processing an output oscillating frequency so as to be completely synchronized with or so as to be the same frequency as the frequency of an input signal or a reference oscillator output signal. Generally, the PLL includes a phase comparator (or a phase detector), a low-pass filter and a voltage controlled oscillator, combined to form a feedback loop.
FIG. 1 illustrates the configuration of a PLL. In FIG. 1, an oscillating frequency of the voltage controlled oscillator 104 is divided by a variable divider 105 and then supplied to a phase comparator 102. The phase comparator 102 compares the phase of the divided oscillating frequency with the phase of a reference signal generated by a reference signal generator 101, and generates a phase difference signal according to a comparison result and outputs it to a low-pass filter 103. Once the signal from the phase comparator 102 is supplied to the voltage controlled oscillator 104 through the low-pass filter 103, the phase of the voltage controlled oscillator 104 varies. Consequently, the voltage controlled oscillator 104 generates a phase locked signal with the reference signal generated by the reference signal generator 101 as an output frequency fvco.
In the PLL as described above, the characteristics of the phase noise of the voltage controlled oscillator 104 and the locking time of the PLL locked with the reference signal are mainly determined by the low-pass filter 103. That is, if the bandwidth of the low-pass filter 103 is widened by adjusting the time constant, the locking time of the PLL is improved but the characteristic of the phase noise is deteriorated since the noise supplied to the voltage controlled oscillator 104 is increased. On the other hand, if the bandwidth of the low-pass filter 103 is narrowed, the characteristic of the phase noise of the voltage controlled oscillator 104 is improved but the locking time of the PLL is lowered.
Meanwhile, in a system in which a dividing value of the variable divider 105 is fixed at one and the voltage controlled oscillator 104 outputs only one oscillating frequency, the locking time of the PLL does not cause great difficulties. However, in a system for alternatively outputting the oscillating frequency of the voltage controlled oscillator 104 via variations of the variable divider 105, the locking time of the PLL must be shortened. For example, a radio telephone or a portable telephone, or a system using a frequency hopping type requires the fast locking time as well as the superior phase noise characteristic of the voltage controlled oscillator.
A method proposed according to such requirements is disclosed in U.S. Pat. No. 4,980,652 issued on Dec. 25, 1990, entitled "Frequency Synthesizer Having Compensation For Nonlinearities". The above U.S. Pat. No. 4,980,652 teaches that a control voltage value corresponding to an output frequency to be obtained in the voltage controlled oscillator is previously stored in a read only memory (hereinafter, referred to as ROM). This voltage value is then used as a control voltage of the voltage controlled oscillator. Also, an error value according to a variation of circumstances such as variations in time and temperature extracted from the low-pass filter is calculated using a drift compensation block and compensated in a subtracter block to be used as the control voltage of the voltage controlled oscillator. Thus, the above U.S. Pat. No. 4,980,652 improves the characteristics of the locking time and the phase noise by using an indirect compensation method that the voltage value previously stored in the ROM is supplied to the voltage controlled oscillator as the control voltage and the voltage value compensated from the subtracter block is supplied to the voltage controlled oscillator as the control voltage.
Meanwhile, in the voltage controlled oscillator of a 900 MHZ band of a commercially available portable telephone, an output frequency deviation caused by variations in ambient temperature is usually .+-.2 MHZ, and the output frequency deviation caused by the component deviation under a constant control voltage of the normal temperature is about .+-.5 MHZ. In other words, the output frequency deviation according to the component deviation of the voltage controlled oscillator and to the variation of circumstances such as variations in time and ambient temperature is above a few thousand PPM (parts per million). When reducing such an output frequency deviation over a few thousand PPM by using the indirect compensation method disclosed in the above U.S. Pat. No. 4,980,652, the system configuration and calculation may be complicated, and a compensation error increased.
Another method proposed for improving the characteristics of the phase noise of the voltage controlled oscillator and the locking time of the PLL is disclosed in U.S. Pat. No. 5,355,098 issued on Oct. 11, 1994, entitled "Phase-Locked Loop with Memory Storing Control Data Controlling the Oscillation Frequency". The above U.S. Pat. No. 5,355,098 teaches that the control voltage supplied to the voltage controlled oscillator immediately before the PLL is powered off is stored in a memory, and the control voltage stored in the memory is used as the control voltage of the voltage controlled oscillator when the PLL is again turned on, thereby improving the characteristics of the phase noise of the voltage controlled oscillator and the locking time of the PLL. However, even though such a method is used, if a long time has elapsed or the ambient temperature varies abruptly, the output frequency deviation according to the variation of circumstances of the voltage controlled oscillator is above a few thousand PPM. That is, since the PLL has an error range caused by a large frequency deviation during initial phase locking, the characteristic of the locking time of the PLL is deteriorated negatively. For example, after the PLL is turned off, when such a long time has elapsed that the component deviation of the voltage controlled oscillator is considerable or when moving to another place having a greatly different ambient temperature, if the power of the PLL is turned on, the output frequency deviation depending on the variation of circumstances is considerable. Accordingly, it takes a long time to lock the initial phase.
The following patents each disclose phase locked loop arrangements having features in common with the present invention. However, none of these patents teaches or suggests the specifically recited combination of features of the present invention: U.S. Pat. No. 4,103,250 to Jackson, entitled Fast Frequency Hopping Synthesizer, U.S. Pat. No. 3,903,482 to Pausini et al., entitled Arrangement For Interference Suppression In Phase Locked Loop Synchronized Oscillators, U.S. Pat. No. 4,677,394 to Vollmer, entitled Method And Apparatus For Calibrating An Adjustable Frequency Generator, U.S. Pat. No. 5,477,194 to Nagakura, entitled Temperature Compensated PLL Frequency Synthesizer And High-Speed Frequency Lock Method Using The Same, U.S. Pat. No. 5,444,420 to Werlund, entitled Numerically Controlled Phase Lock Loop Synthesizer/Modulator And Method, U.S. Pat. No. 5,367,269 to Yanagidaira et al., entitled System for Producing An Oscillating Jamming Signal Utilizing A Phase-Locked Loop, U.S. Pat. No. 5,389,899 to Yahagi et al., entitled Frequency Synthesizer Having Quick Frequency Pull In And Phase Lock-In, U.S. Pat. No. 5,184,092 to Shahriary et al., entitled Phase-Locked Loop Frequency Tracking Device Including A Direct Digital Synthesizer, U.S. Pat. No. 4,629,999 to Hatch et al., entitled Phase-Locked Loop Capable Of Generating A Plurality Of Stable Frequency Signals, U.S. Pat. No. 5,036,295 to Kamitani, entitled Frequency Synthesizer Allowing Rapid Frequency Switching, U.S. Pat. No. 4,864,253 to Zwack, entitled Phase Locked Loop Wherein Phase Comparing And Filtering Are Performed By Microprocessor, U.S. Pat. No. 4,980,652 to Tarusawa et al., entitled Frequency Synthesizer Having Compensation For Nonlinearities, U.S. Pat. No. 5,355,098 to Iwasaki, entitled Phase-Locked Loop With Memory Storing Control Data controlling The Oscillation Frequency, U.S. Pat. No. 5,561,400 to Iguchi et al., entitled Oscillator Unit, U.S. Pat. No. 3,854,102 to Seipel et al., entitled Multiple Frequency Band Frequency Synthesizer, U.S. Pat. No. 5,059,924 to JenningsCheck, entitled Clock Adapter Using A Phase Locked Loop Configured As A Frequency Multiplier With A Non-Integer Feedback Divider, U.S. Pat. No. 5,055,801 to Koga et al., entitled Digital Phase Locked Loop For Correcting A Phase Of An Output Signal With Respect To An Input Signal, U.S. Pat. No. 5,055,800 Black et al., entitled Fractional NIMSynthesis, U.S. Pat. No. 5,028,885 to Voigt et al., entitled Phase-Locked Loop Signal Generafion System With Control Maintenance, U.S. Pat. No. 4,942,371 to Kashiwaba et al., entitled Phase-Locked Loop Having Improved Input Jitter Characteristics, U.S. Pat. No. 4,816,774 to Martin, entitled Frequency Synthesizer With Spur Compensation, U.S. Pat. No. 4,135,166 to Marchetti, entitled Master Timing Generator, U.S. Pat. No. 4,336,616 to Carson et al., entitled Discriminator Aided Phase Lock Acquisition For Suppressed Carrier Signals, U.S. Pat. No. 4,752,749 to Moger, entitled Fast Response Tuner, U.S. Pat. No. 5,146,187 to Vandegraaf, entitled Synthesizer Loop Filter For Scanning Receivers, U.S. Pat. No. 5,068,752 to Tanaka et al., entitled Apparatus For Recording/Reproducing A Digital Audio Signal With A Video Signal, U.S. Pat. No. 5,170,130 to Ichihara, entitled Phase Lock Loop Circuit With A Subsidiary Loop Filter U.S. Pat. No. 5,272,452 to Adachi et al., entitled PLL Frequency Synthesizer With Variable Bandwidth Loop Filter, U.S. Pat. No. 5,557,648 to Ishihara, entitled Phase Lock Loop Circuit Using A Sample And Hold Switch Circuit and U.S. Pat. No. 3,989,690 to Desai, entitled Phase-Locked Loop For An Electronic Sectoring Schemie For Rotating Magnetic Memory.